Teaching field: 

The objective of this course is to give an expertise of design and verification of digital systems. The students will learn the VHDL language and they will use the FPGA Xilinx Spartan II to realize an industrial–like project. Lectures are given in english.

The course will start with the design flow of a digital system. Next we will present the VHDL language with its specificity: concurrent language, the concepts of process and signal, the genericity of VHDL constructions. The RTL synthesis and the performance analysis, specifically the timing analysis will be detailed. The laboratory classes will be organized in two parts: the first one will illustrate directly the knowledge presented in the course and the second one will be organized like a project. The students will develop an Ethernet controller respecting the real specification of the IEEE 802. 3 standard and the CSMA/CD protocol.

SoPC - VHDL / FPGA826.88 KB
Ethernet 10 - Technical Manual480.39 KB
TP Compteur20.67 KB
VHDL_analyseur_logique.pdf194.13 KB