Teaching field: 
5 SE

Introduction to the Systems on Chip (SoC) and Systems on Programmable Chip (SoPC) design and learning of the VLSI design flow for mixed signal ASIC: digital– analog– RF

An introduction to the SoC and SoPC design is presented during the lectures. The design of digital ASICs and analog ASICs with extension to RF circuits and their integration on the same chip is realized during the laboratory classes.

Laboratories: The first part is dedicated to a complete design of a digital ASIC from the VHDL code, to RTL synthesis, and then to place and route the ASIC on a silicon chip. The labs are given using a real design kit from an industrial foundry, the CADENCE platform ( IUS– VHDL simulation, SoCencounter– place and route tool) and SYNOPSYS
platform ( Design Compiler – RTL synthesis tool). In the second part the complete analog design of a oscillator is realized up to 1GHz using the same design kit and the CADENCE analog design tools. The integration on the same silicon chip of the digital and analog circuits is done during the last session.

SoC_SystemC_2010_complet.pdf1.6 MB
eth_test.vhd6.35 KB
Ethernet10 _avec_signaux_barrés.pdf480.39 KB
SoC_SystemC_2012_anglais.pdf1.56 MB
cours_VHDL_final_4AE.pdf826.83 KB
2014TP_AMS_SoCencounter_DesignCompiler.pdf1.01 MB