A new research project with CNES (French Spatial Agency) and Thales Alenia Space will start in October 2013 for 3 years on the topic:

Development of a Core-chip MMIC solution integrated in BiCMOS technology for beamforming satellite antenna

   A Ph.D. position will be opened on this project. The firm dead-line for application is: 25 March 2013


Development of a Core-chip MMIC solution integrated in BiCMOS technology for beamforming satellite antenna

 Open Ph.D. position

 

Ph. D. Advisor:  Associate Professor Daniela Dragomirescu, University of Toulouse, LAAS-CNRS

Ph.D. funding: joint between Thales Alenia Space and French Spatial Agency (CNES)

Firm dead-line for applications :  25 March 2013

 

            This PH.D. subject concerns the design and realization of a Core-chip MMIC system with serial to parallel converter integrated in SiGe BiCMOS technology. This core-chip MMIC system is dedicated to the beamforming for the active satellite antenna. The new solutions for the satellite payloads being developed for telecommunication applications need an increased flexibility at all the levels. More precisely, the system of active antennas allowing an adjustment by real-time electronic command of the terrestrial covered area offers an optimized response for the communication link budget. This performance has a cost: the necessity of a very large number of RF control points "amplitude / phase" of the beamforming equipment which power the active antenna matrix elements. So, it becomes mandatory to bring a new solution to optimize this function. The main challenges are: increasing the functions integration, decreasing the DC power consumption and keeping the RF performances in terms of gain, resolution and linearity.

            In this context, the SiGe technologies propose technological and topological efficient solutions for the RF system and for the digital command circuit. The major goal is to design a complete system in order to form a homogeneous polar constellation diagram for minimizing the error for any couple of amplitude and phase.

            The intended application is the beamforming for active antennas. A large number of controls nodes per device are required. The integration capability on the silicon chip is a key issue allowing a significant footprint reduction beside the low power consumption’s target for active antennas. The maximum size/ MMIC chip should be less than 4 x 4 mm2. The feasibility of the multi-node chips development will be also investigated in order to minimize the number of active antennas and consequently to increase the system integration level.

An exhaustive analyze of the state-of-art existing topologies will be performed with a focus on the following aspects:

  • investigation of the different architecture for RF front-end module: polar or vectorial solution
  • investigation of the optimal solution for switch actuation. Several technologies such as bipolar, CMOS or MEMS should be analyzed and the best solution will be retained (as function of insertion loss and isolation performances). The use of the slow-wave transmission lines should be envisaged.
  • investigation of the best topology for command unit: fully analog architecture  versus ADC (analog-to-digital converter) based solution (main criteria of the selection : circuit complexity/DC power consumption)

        A solution based on the use of slow-wave transmission line fully compatible with the CMOS technology will be carefully investigated in order to improve the architecture of the phase-shifter circuits.

        IHP company was identified as a possible manufacturing for the demonstrators (IHP already engaged a qualification procedure for space applications with the support of ESA through SGB25V process). IHP technologies allow the integration of the MEMS capacitive switches on a silicon chip. Consequently, the BiCMOS (0.25 µm, 0.13 µm, etc.) technologies from IHP and their capabilities will be analyzed. Alternative manufacturing technologies from others companies should also be considered for comparison. The core-chip MMIC will be designed according to the following criteria:

-       frequency band : X, Ku, Ka

-       relative bandwidth : 20 à 40 %

-       8 bits (amplitude) + 8 bits (phase) for phase/amplitude constellation diagram

-       dynamic range : 24 dB (amplitude), 360° (phase)

-       minimizing the insertion losses, DC power consumption, the radiation and temperature sensitivity

-       increasing the linearity and RF power capabilities

-       reducing the circuit footprint

 Job/Candidate profile

Graduate student in Electrical Engineering/Electronics (master, engineering school, etc.) with a strong background in the field of silicon based RFIC/MMIC/ASIC circuit design and RF/microwave engineering. A previously experience in the design and the characterization of RF/microwave circuits and with CAD tools for RFIC/ASIC circuit design (Cadence, ADS, etc.) or for electromagnetic simulation (HFSS, Sonnet, etc.) will be appreciated.