| May 18, 2006 |
|
| Tutorials | |
| 9:00-10:00 |
EMI
immunity issues in
integrated circuits: an overview of measurement methods and current
studies - M. Ramdani,
ESEO
(France) |
| 10:00-10:30 |
Break |
| 10:30-12:30 |
ESD
protection for advanced CMOS
technologies - H.
Gossner, Infineon (Germany) |
| 1:00-2:00 | LUNCH |
| Session 1A:
ESD protection challenges in advanced technologies |
|
| 2:00-2:10 | Introduction |
| 2:10-2:50 |
1.1-Invited: Review of Approaches
and Solutions for Effective ESD Protection Devices and Schemes in Smart
Power ICs - A.
Andreini, L. Cerati and G. Meneghesso, STMicroelectronics and University of
Padova (Italy) |
| 2:50-3:10 | 1.2: Impact of new technology options on the ESD robustness of sub- 45 nm FinFET technology - D. Trémouilles, M.I. Natarajan, D. Linten, M. Scholz and G. Groeseneken, IMEC (Belgium) |
| 3:10-3:30 | 1.3: ESD protection network development in advanced 65nm CMOS technologies - J.P. Lainé, S. Ruth, A. Dray and M. Zécri, Crolles2 Alliance (France) |
| 3:30-3:50 | 1.4: Comparison of efficient solutions for the ESD Protection of High-Voltage I/Os in Advanced Smart Power Technology - A. Gendron, C. Salamero, N. Nolhier, M. Bafleur, P. Renaud and P. Besse, Freescale and LAAS/CNRS (France) |
| 3:50-4:20 | Break |
| Session 1B: ESD
characterization |
|
| 4:20-4:40 | 1.5: Comparing arc-free Capacitive Coupled Transmission Line Pulsing CC-TLP with Standard CDM Testing and CDM Field Failures - ESD German Forum Best award paper - H. Gieser, H. Wolf and F. Iberl, IZM-M/ATIS (Germany) |
| 4:40-5:00 | 1.6:
Can HBM tester replace 100ns TLP
tester? - M. Scholz,
D. Trémouilles, M.I. Natarajan, M. Sawada, T. Nakaei, T. Hasebe
and G. Groeseneken, IMEC and Hanwa Electronics (Belgium) |
| 5:00-5:20 | 1.7: Deriving the DUT Current and Voltage Waveforms by Merging VF-TLP Incident and Reflected Signals - E. Grund, Lee Walsh ORYX Instruments (CA, USA) |
| 5:20-5:50 | Equipement
demonstration: Very
Fast TLP with TDR signal processing at wafer level - ORYX Instruments
and MB Electronique |
| 5:50-6:30 | Round
Table: ESD
characterization techniques, which one to choose? |
| 7:30-11:30 | BANQUET downtown Toulouse |
| May 19, 2006 |
|
| Session 2A : EMI and System level ESD | |
| 9:00-9:40 | 2.1-Invited: EMI-induced failures in integrated circuits operation - F. Fiori, University of Torino (Italy) |
| 9:40-10:00 | 2.2: Kuijk Bandgap Susceptibility to RF Interferences: Measurements, Modeling and Provisions - E. Orietti, N. Montemezzo, S. Buso, A. Neviani, G. Meneghesso and G. Spiazzi, University of Padova (Italy) |
| 10:00-10:20 | 2.3: Original methodology for Integrated Circuit ESD immunity combining VF-TLP and near field scan testing - N. Lacrampe, A. Boyer, N. Nolhier, F. Caignet and M. Bafleur, LAAS/CNRS and LEISA/INSA (France) |
| 10:20-11:00 | Round
Table: ESD and EMI immunity issues, convergences and divergences |
| 11:00-11:20 | Break |
| Session 2B : EMI and System level ESD (cont.) | |
| 11:20-12:00 | 2.4-Invited: Power by wire, an opportunity? - E. Foch, Airbus (France) |
| 12:00-12:20 | 2.5: EMC considerations in the European Program MOET - R. Perraud, O. Maurice and G. Peres, EADS-CCR (France) |
| 12:20-12:40 | 2.6: Common mode ESD tests at equipment or subsystem level - J.P. Catani, CNES (France) |
| 1:00-2:00 | LUNCH |
| Session 3 : ESD Failure analysis &
Simulation |
|
| 2:00-2:40 | 3.1-Invited: Electrostatic Discharge From Outside to Surface (ESDFOS) As A Yield and Reliability Risk in Microstructure Assembly Processing - P. Jacob and A. Kunz, EMPA (Switzerland) |
| 2:40-3:00 | 3.2: Snapback in well resistors during ESD - G. Notermans, A. Heringa, O. Quittard and F. Blanc, Philips AG (Switzerland) |
| 3:00-3:20 | 3.3: OBIC technique for ESD defect localization: Influence of the experimental procedure - F. Essely, N. Guitard, F. Darracq, V. Pouget, M. Bafleur, A. Touboul and D. Lewis, IXL, LAAS/CNRS and CNES (France) |
| 3:20-3:40 | 3.4: Overvoltage during FTLP compared to TLP on a single finger grounded gate nMOS transistor - P. Galy, V.Berland , M. Bafleur and N. Nolhier, ST-Microelectronics, Pole Universitaire Léonard de Vinci, LORE and LAAS/CNRS (France) |
| 3:40-4:00 | 3.5: A simulation tool for CDM stress evaluation at circuit level, M. Lafont, F. Azais, P. Galy, P. Salomé and P. Nouet, LIRMM, STMicroelectronics and SERMA Technologies (France) |
| 4:00-4:30 | Conclusions |