Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.5 (WebPack) - P.58f Target Family: Spartan3
OS Platform: LIN64 Target Device: xc3s1000
Project ID (random number) e051c2a4a5894005a350e429db1a6d1a.9E494D1A521535222D1D710A8D0CA7A5.3 Target Package: ft256
Registration ID 210817420_0_0_930 Target Speed: -4
Date Generated 2013-12-13T19:06:31 Tool Flow ISE
 
User Environment
OS Name Ubuntu OS Release Ubuntu 12.04.3 LTS
CPU Name Intel(R) Xeon(R) CPU E5-1650 0 @ 3.20GHz CPU Speed 1200.000 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=8
  • 2-bit adder=1
  • 29-bit adder=2
  • 29-bit subtractor=1
  • 31-bit adder=1
  • 32-bit adder=1
  • 4-bit adder=2
 Comparators=29
  • 10-bit comparator less=1
  • 11-bit comparator greatequal=2
  • 11-bit comparator less=23
  • 11-bit comparator lessequal=2
  • 33-bit comparator greatequal=1
 Counters=6
  • 10-bit up counter=2
  • 2-bit down counter=1
  • 32-bit up counter=1
  • 5-bit up counter=1
  • 7-bit down counter=1
 FSMs=3 Latches=5
  • 16-bit latch=1
  • 18-bit latch=1
  • 3-bit latch=1
  • 32-bit latch=1
  • 8-bit latch=1
 Multiplexers=3
  • 1-bit 8-to-1 multiplexer=1
  • 32-bit 4-to-1 multiplexer=1
  • 8-bit 4-to-1 multiplexer=1
 RAMs=1
  • 2048x8-bit single-port block RAM=1
 Registers=455
  • Flip-Flops=455
 		MiscellaneousStatistics
  • AGG_BONDED_IO=81
  • AGG_IO=81
  • AGG_SLICE=748
  • NUM_4_INPUT_LUT=1086
  • NUM_BONDED_IOB=81
  • NUM_BUFGMUX=4
  • NUM_CARRY_SKIP=1
  • NUM_CYMUX=189
  • NUM_IOB_LATCH=8
  • NUM_LUT_RT=87
  • NUM_RAMB16=9
  • NUM_SLICEL=748
  • NUM_SLICE_FF=524
  • NUM_SLICE_LATCH=77
  • NUM_XOR=185
 		NetStatistics
  • NumNets_Active=1676
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=203
  • NumNodesOfType_Active_BRAMDUMMY=64
  • NumNodesOfType_Active_CLKPIN=411
  • NumNodesOfType_Active_CNTRLPIN=769
  • NumNodesOfType_Active_DOUBLE=4038
  • NumNodesOfType_Active_DUMMY=3458
  • NumNodesOfType_Active_DUMMYBANK=130
  • NumNodesOfType_Active_DUMMYESC=32
  • NumNodesOfType_Active_GLOBAL=155
  • NumNodesOfType_Active_HFULLHEX=82
  • NumNodesOfType_Active_HLONG=14
  • NumNodesOfType_Active_HUNIHEX=453
  • NumNodesOfType_Active_INPUT=4093
  • NumNodesOfType_Active_IOBOUTPUT=32
  • NumNodesOfType_Active_OMUX=1404
  • NumNodesOfType_Active_OUTPUT=1564
  • NumNodesOfType_Active_PREBXBY=1239
  • NumNodesOfType_Active_VFULLHEX=282
  • NumNodesOfType_Active_VLONG=55
  • NumNodesOfType_Active_VUNIHEX=400
  • NumNodesOfType_Gnd_CNTRLPIN=18
  • NumNodesOfType_Gnd_DOUBLE=27
  • NumNodesOfType_Gnd_HFULLHEX=2
  • NumNodesOfType_Gnd_INPUT=10
  • NumNodesOfType_Gnd_OMUX=22
  • NumNodesOfType_Gnd_OUTPUT=18
  • NumNodesOfType_Gnd_PREBXBY=7
  • NumNodesOfType_Gnd_VFULLHEX=3
  • NumNodesOfType_Vcc_CNTRLPIN=21
  • NumNodesOfType_Vcc_INPUT=9
  • NumNodesOfType_Vcc_PREBXBY=9
  • NumNodesOfType_Vcc_VCCOUT=20
 SiteStatistics
  • IOB-DIFFM=33
  • IOB-DIFFS=41
  • SLICEL-SLICEM=375
 		SiteSummary
  • BUFGMUX=4
  • BUFGMUX_GCLKMUX=4
  • BUFGMUX_GCLK_BUFFER=4
  • IOB=81
  • IOB_INBUF=32
  • IOB_OFF1=8
  • IOB_OUTBUF=65
  • IOB_PAD=81
  • RAMB16=9
  • RAMB16_RAMB16=9
  • RAMB16_RAMB16A=9
  • RAMB16_RAMB16B=8
  • SLICEL=748
  • SLICEL_C1VDD=19
  • SLICEL_C2VDD=19
  • SLICEL_CYMUXF=97
  • SLICEL_CYMUXG=92
  • SLICEL_F=538
  • SLICEL_F5MUX=31
  • SLICEL_F6MUX=1
  • SLICEL_FFX=263
  • SLICEL_FFY=338
  • SLICEL_G=548
  • SLICEL_GNDF=59
  • SLICEL_GNDG=55
  • SLICEL_VDDG=1
  • SLICEL_XORF=94
  • SLICEL_XORG=91
 
Configuration Data
BUFGMUX
  • S=[S_INV:4] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:4]
  • S=[S_INV:4] [S:0]
 IOB
  • O1=[O1_INV:8] [O1:57]
  • OCE=[OCE:8] [OCE_INV:0]
  • OTCLK1=[OTCLK1_INV:8] [OTCLK1:0]
  • SR=[SR:8] [SR_INV:0]
  • T1=[T1_INV:0] [T1:16]
 IOB_OFF1
  • CE=[CE:8] [CE_INV:0]
  • CK=[CK:0] [CK_INV:8]
  • D=[D:8] [D_INV:0]
  • LATCH_OR_FF=[LATCH:8]
  • OFF1_INIT_ATTR=[INIT0:8]
  • OFF1_SR_ATTR=[SRLOW:8]
  • OFFATTRBOX=[ASYNC:8]
  • SR=[SR:8] [SR_INV:0]
 IOB_OUTBUF
  • IN=[IN_INV:8] [IN:57]
  • TRI=[TRI_INV:0] [TRI:16]
 IOB_PAD
  • DRIVEATTRBOX=[8:6] [12:59]
  • IOATTRBOX=[LVCMOS25:42] [LVCMOS33:39]
  • SLEW=[SLOW:21] [FAST:44]
 RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:9]
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • ENA=[ENA_INV:0] [ENA:9]
  • ENB=[ENB_INV:0] [ENB:8]
  • SSRA=[SSRA_INV:0] [SSRA:9]
  • SSRB=[SSRB_INV:0] [SSRB:8]
  • WEA=[WEA:9] [WEA_INV:0]
  • WEB=[WEB:8] [WEB_INV:0]
 RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:9]
  • ENA=[ENA_INV:0] [ENA:9]
  • PORTA_ATTR=[2048X9:1] [4096X4:8]
  • SSRA=[SSRA_INV:0] [SSRA:9]
  • WEA=[WEA:9] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:9]
 RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • ENB=[ENB_INV:0] [ENB:8]
  • PORTB_ATTR=[4096X4:8]
  • SSRB=[SSRB_INV:0] [SSRB:8]
  • WEB=[WEB:8] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:8]
 SLICEL
  • BX=[BX_INV:8] [BX:190]
  • BY=[BY:238] [BY_INV:6]
  • CE=[CE:184] [CE_INV:49]
  • CIN=[CIN_INV:0] [CIN:91]
  • CLK=[CLK:334] [CLK_INV:52]
  • SR=[SR:285] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:97] [0_INV:0]
  • 1=[1_INV:1] [1:96]
 SLICEL_CYMUXG
  • 0=[0:91] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:29] [S0_INV:2]
 SLICEL_F6MUX
  • S0=[S0:0] [S0_INV:1]
 SLICEL_FFX
  • CE=[CE:159] [CE_INV:43]
  • CK=[CK:213] [CK_INV:50]
  • D=[D:258] [D_INV:5]
  • FFX_INIT_ATTR=[INIT0:251] [INIT1:12]
  • FFX_SR_ATTR=[SRLOW:246] [SRHIGH:17]
  • LATCH_OR_FF=[FF:225] [LATCH:38]
  • REV=[REV_INV:0] [REV:2]
  • SR=[SR:179] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:189] [SYNC:74]
 SLICEL_FFY
  • CE=[CE:160] [CE_INV:40]
  • CK=[CK:287] [CK_INV:51]
  • D=[D:333] [D_INV:5]
  • FFY_INIT_ATTR=[INIT0:314] [INIT1:24]
  • FFY_SR_ATTR=[SRLOW:313] [SRHIGH:25]
  • LATCH_OR_FF=[FF:299] [LATCH:39]
  • REV=[REV_INV:0] [REV:61]
  • SR=[SR:247] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:190] [SYNC:148]
 SLICEL_XORF
  • 1=[1_INV:1] [1:93]
 
Pin Data
BUFGMUX
  • I0=4
  • O=4
  • S=4
 BUFGMUX_GCLKMUX
  • I0=4
  • OUT=4
  • S=4
 BUFGMUX_GCLK_BUFFER
  • IN=4
  • OUT=4
 IOB
  • I=32
  • O1=65
  • OCE=8
  • OTCLK1=8
  • PAD=81
  • SR=8
  • T1=16
 IOB_INBUF
  • IN=32
  • OUT=32
 IOB_OFF1
  • CE=8
  • CK=8
  • D=8
  • Q=8
  • SR=8
 IOB_OUTBUF
  • IN=65
  • OUT=65
  • TRI=16
 IOB_PAD
  • PAD=81
 RAMB16
  • ADDRA10=9
  • ADDRA11=9
  • ADDRA12=9
  • ADDRA13=9
  • ADDRA2=8
  • ADDRA3=9
  • ADDRA4=9
  • ADDRA5=9
  • ADDRA6=9
  • ADDRA7=9
  • ADDRA8=9
  • ADDRA9=9
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB2=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=9
  • CLKB=8
  • DIA0=8
  • DIA1=8
  • DIA2=8
  • DIA3=8
  • DIB0=8
  • DIB1=8
  • DIB2=8
  • DIB3=8
  • DOA0=9
  • DOA1=9
  • DOA2=9
  • DOA3=9
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOB0=8
  • DOB1=8
  • DOB2=8
  • DOB3=8
  • ENA=9
  • ENB=8
  • SSRA=9
  • SSRB=8
  • WEA=9
  • WEB=8
 RAMB16_RAMB16
  • ADDRA=9
  • ADDRB=8
  • DIA=9
  • DIB=8
  • DOA=9
  • DOB=8
 RAMB16_RAMB16A
  • ADDRA=9
  • ADDRA10=9
  • ADDRA11=9
  • ADDRA12=9
  • ADDRA13=9
  • ADDRA2=8
  • ADDRA3=9
  • ADDRA4=9
  • ADDRA5=9
  • ADDRA6=9
  • ADDRA7=9
  • ADDRA8=9
  • ADDRA9=9
  • CLKA=9
  • DIA=9
  • DIA0=8
  • DIA1=8
  • DIA2=8
  • DIA3=8
  • DOA=9
  • DOA0=9
  • DOA1=9
  • DOA2=9
  • DOA3=9
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • ENA=9
  • SSRA=9
  • WEA=9
 RAMB16_RAMB16B
  • ADDRB=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB2=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKB=8
  • DIB=8
  • DIB0=8
  • DIB1=8
  • DIB2=8
  • DIB3=8
  • DOB=8
  • DOB0=8
  • DOB1=8
  • DOB2=8
  • DOB3=8
  • ENB=8
  • SSRB=8
  • WEB=8
 SLICEL
  • BX=198
  • BY=244
  • CE=233
  • CIN=91
  • CLK=386
  • COUT=92
  • F1=534
  • F2=473
  • F3=367
  • F4=302
  • F5=2
  • FXINA=1
  • FXINB=1
  • G1=546
  • G2=486
  • G3=404
  • G4=332
  • SR=285
  • X=433
  • XQ=263
  • Y=359
  • YQ=338
 SLICEL_C1VDD
  • 1=19
 SLICEL_C2VDD
  • 1=19
 SLICEL_CYMUXF
  • 0=97
  • 1=97
  • OUT=97
  • S0=97
 SLICEL_CYMUXG
  • 0=91
  • 1=92
  • OUT=92
  • S0=92
 SLICEL_F
  • A1=534
  • A2=473
  • A3=367
  • A4=302
  • D=538
 SLICEL_F5MUX
  • F=31
  • G=31
  • OUT=31
  • S0=31
 SLICEL_F6MUX
  • 0=1
  • 1=1
  • OUT=1
  • S0=1
 SLICEL_FFX
  • CE=202
  • CK=263
  • D=263
  • Q=263
  • REV=2
  • SR=179
 SLICEL_FFY
  • CE=200
  • CK=338
  • D=338
  • Q=338
  • REV=61
  • SR=247
 SLICEL_G
  • A1=546
  • A2=486
  • A3=404
  • A4=332
  • D=548
 SLICEL_GNDF
  • 0=59
 SLICEL_GNDG
  • 0=55
 SLICEL_VDDG
  • 1=1
 SLICEL_XORF
  • 0=94
  • 1=94
  • O=94
 SLICEL_XORG
  • 0=91
  • 1=91
  • O=91
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 4 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 1 1 0 0 0 0 0
bitgen 2 2 0 0 0 0 0
map 3 2 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngdbuild 26 25 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 2 2 0 0 0 0 0
xst 9 9 0 0 0 0 0
 
Project Statistics
PROP_CompxlibOverwriteLib=true PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PostTrceFastPath=false PROP_PreTrceFastPath=false
PROP_PropSpecInProjFile=Store all values PROP_SimModelInsertBuffersPulseSwallow=false
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserBrowsedStrategyFiles=/opt/Xilinx/14.5/ISE_DS/ISE/data/default.xds PROP_UserConstraintEditorPreference=Text Editor
PROP_XPowerOptLoadXMLFile=changed PROP_XPowerOptOutputFile=changed
PROP_intProjectCreationTimestamp=2013-12-11T10:52:16 PROP_intWbtProjectID=9E494D1A521535222D1D710A8D0CA7A5
PROP_intWbtProjectIteration=3 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_xilxPostTrceRpt=Error Report
PROP_AutoTop=true PROP_DevFamily=Spartan3
PROP_MapEffortLevel=Standard PROP_DevDevice=xc3s1000
PROP_DevFamilyPMName=spartan3 PROP_DevPackage=ft256
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=VHDL FILE_BMM=1
FILE_UCF=1 FILE_VHDL=22
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=38 NGDBUILD_NUM_FDCE=85
NGDBUILD_NUM_FDE=175 NGDBUILD_NUM_FDP=3 NGDBUILD_NUM_FDPE=1 NGDBUILD_NUM_FDR=53
NGDBUILD_NUM_FDRE=52 NGDBUILD_NUM_FDRE_1=8 NGDBUILD_NUM_FDRS=59 NGDBUILD_NUM_FDRSE=1
NGDBUILD_NUM_FDR_1=11 NGDBUILD_NUM_FDS=35 NGDBUILD_NUM_FDSE=3 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=14 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=57 NGDBUILD_NUM_IOBUF=16
NGDBUILD_NUM_LDCE=82 NGDBUILD_NUM_LDCPE=3 NGDBUILD_NUM_LUT1=86 NGDBUILD_NUM_LUT2=174
NGDBUILD_NUM_LUT2_D=6 NGDBUILD_NUM_LUT2_L=1 NGDBUILD_NUM_LUT3=125 NGDBUILD_NUM_LUT3_D=10
NGDBUILD_NUM_LUT3_L=9 NGDBUILD_NUM_LUT4=497 NGDBUILD_NUM_LUT4_D=20 NGDBUILD_NUM_LUT4_L=117
NGDBUILD_NUM_MUXCY=188 NGDBUILD_NUM_MUXF5=31 NGDBUILD_NUM_MUXF6=1 NGDBUILD_NUM_OBUF=49
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=185
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_FDC=38 NGDBUILD_NUM_FDCE=85 NGDBUILD_NUM_FDE=175
NGDBUILD_NUM_FDP=3 NGDBUILD_NUM_FDPE=1 NGDBUILD_NUM_FDR=53 NGDBUILD_NUM_FDRE=52
NGDBUILD_NUM_FDRE_1=8 NGDBUILD_NUM_FDRS=59 NGDBUILD_NUM_FDRSE=1 NGDBUILD_NUM_FDR_1=11
NGDBUILD_NUM_FDS=35 NGDBUILD_NUM_FDSE=3 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=30
NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_INV=57 NGDBUILD_NUM_LDCE=82 NGDBUILD_NUM_LDCPE=3
NGDBUILD_NUM_LUT1=86 NGDBUILD_NUM_LUT2=174 NGDBUILD_NUM_LUT2_D=6 NGDBUILD_NUM_LUT2_L=1
NGDBUILD_NUM_LUT3=125 NGDBUILD_NUM_LUT3_D=10 NGDBUILD_NUM_LUT3_L=9 NGDBUILD_NUM_LUT4=497
NGDBUILD_NUM_LUT4_D=20 NGDBUILD_NUM_LUT4_L=117 NGDBUILD_NUM_MUXCY=188 NGDBUILD_NUM_MUXF5=31
NGDBUILD_NUM_MUXF6=1 NGDBUILD_NUM_OBUF=49 NGDBUILD_NUM_OBUFT=16 NGDBUILD_NUM_RAMB16_S4_S4=8
NGDBUILD_NUM_RAMB16_S9=1 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=185
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s1000-4-ft256 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5