Project Statistics |
PROP_CompxlibOverwriteLib=true |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PostTrceFastPath=false |
PROP_PreTrceFastPath=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SimModelInsertBuffersPulseSwallow=false |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=/opt/Xilinx/14.5/ISE_DS/ISE/data/default.xds |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_XPowerOptLoadXMLFile=changed |
PROP_XPowerOptOutputFile=changed |
PROP_intProjectCreationTimestamp=2013-12-11T10:52:16 |
PROP_intWbtProjectID=9E494D1A521535222D1D710A8D0CA7A5 |
PROP_intWbtProjectIteration=3 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxPostTrceRpt=Error Report |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3 |
PROP_MapEffortLevel=Standard |
PROP_DevDevice=xc3s1000 |
PROP_DevFamilyPMName=spartan3 |
PROP_DevPackage=ft256 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=VHDL |
FILE_BMM=1 |
FILE_UCF=1 |
FILE_VHDL=22 |