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Abstract
This paper addresses the resilience challenges in the future nanochips
made up of massively defective nanoelements and organized in a replicative
multicore architecture. The main idea is to suggest that the chip
should work with almost no external testing or control mechanisms,
using a self-configuration methodology to ensure the resilience of
operation even in the presence of a significant fraction of defective
cores. By self–configuration, we mean self-diagnosis with mutual
tests, self-shutdown of inactive cores and self-configuration of communications.
We study the efficiency of the proposed methodology and show that the
method is applicable up to a fraction of 30% of defective cores in
the on-chip network.
Keywords: Nanoscale chips, muticore processor
architectures, resilience, self-reconfiguration
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